1. Field of the Invention
The present invention relates generally to semiconductor devices and methods of fabricating the same and, more particularly, to metal oxide semiconductor (MOS) field effect transistors (hereinafter referred to as MOS transistors) and methods of fabricating the same.
2. Description of Related Art
In general, semiconductor devices use discrete devices, such as MOS transistors as switching devices. With an increase in the degree of integration of semiconductor devices, the MOS transistor is being gradually scaled down. As a result, a MOS transistor with a typical horizontal channel may not operate normally due to a short channel effect (SCE) and a drain-induced barrier lowering (DIBL) effect, which may be caused by a short channel length between a source and a drain. Also, owing to increases in off current and swing, it may be difficult to effectively control the on/off operation of the MOS transistor.
To overcome the foregoing drawbacks of a MOS transistor with a horizontal channel, other MOS transistors having various structures have been proposed. One of the new MOS transistors is a double gate transistor, an example of which is described in U.S. Pat. No. 6,355,532. In the double gate transistor, a gate electrode surrounds two or three sides of a channel such that all of the regions of the channel are affected by the gate electrode. This may lead to reductions in swing and off current, which are subthreshold characteristics. As a result, when the MOS transistor is turned off, it may be possible to regulate the flow of electric charges between a source and a drain so that power dissipation can be reduced and the on/off operation of the MOS transistor can be effectively controlled.
In another approach to address the problems of a MOS transistor with a horizontal channel, there have been intensive studies on a MOS transistor having a recessed gate electrode called a “trench-gate transistor” (hereinafter a recess gate transistor) as another new MOS transistor. The recess gate transistor, an example of which is described in U.S. Pat. No. 6,498,071, includes a recess formed in an active region of a semiconductor substrate, a gate electrode formed in the recess, and source and drain regions that are formed in the active region on both sides of the gate electrode and spaced apart from each other by to the recess. In spite of the relatively high degree of integration, such a recess gate transistor may suppress the influence of a short channel effect (SCE) and a drain-induced barrier lowering (DIBL) effect due to its increased channel length.
However, a recess of a conventional recess gate transistor, which is formed in an active region by etching a silicon substrate exposed by a mask pattern, typically has a flat or concave bottom profile in the direction of channel width. As a result, although the influence of the SCE and DIBL effect may be suppressed, there is a limit in improving a swing or off current characteristic with an increase in the capacitance of a depletion layer due to a gate voltage.